1. Field of the Invention
The present invention relates to an apparatus for detecting the rotation speed of a rotatory body or member such as a rotary shaft of an electric motor.
The speed detecting apparatus according to the invention is usually incorporated in a speed control system to constitute, for example, a motor speed change arrangement such as thyristor Leonard equipment in a steel plant or the like.
2. Description of the Prior Art
FIG. 3 is a block diagram of a control system relative to a conventional speed detecting apparatus, in which there are shown a DC motor 11, an apparatus 12 for detecting the rotation speed of the DC motor 11, and a speed controller 13 for producing a reference current which corresponds to the difference between a set speed and the actual speed detected by the apparatus 12. Further shown are a three-phase AC source 14, a power rectifier 15 for converting a three-phase AC into a variable DC voltage, a current sensor 16 for sensing the current value supplied to the power rectifier 15, a current controller 17 for providing data to adjust the output voltage of the power rectifier 15 in accordance with the difference between the actual current obtained from the current sensor 16 and the reference current produced from the speed controller 13, and a gate control circuit 18 for controlling switching elements such as thyristors of the power rectifier 15 in conformity with the data from the current controller 17. The rotation speed of the DC motor 11 is controlled by changing the voltage applied thereto. The power rectifier 15 is assumed to be capable of selectively functioning in a positive voltage output mode or a negative voltage output mode in accordance with the reference current outputted from the speed controller 13.
In the constitution mentioned above, the following operation is performed. Generally the control response in such circuit configuration is enhanced as the sampling time for speed detection is shortened. However, due to the play existing inevitably in any mechanism such as gears, great pulsation is induced in the speed to be detected when the sampling time is short, and therefore the reference current value obtained from the speed controller 13 also pulsates to a considerable extent. In case the load is light to consequently require generation of a small torque, the mean current value is small so that there occurs a state where the reference current pulsates between a positive value and a negative value as a result of the speed pulsation. Accordingly, the power rectifier 15 comes to be frequently switched for generation of a positive voltage or a negative voltage, and the control system is rendered unstable by such wasteful switching time and so forth.
Meanwhile, if the sampling time is prolonged, momentary great pulsation is absorbed in the mean value to eventually reduce the variation in the speed to be detected, whereby the control system is stabilized. Practically, however, a great torque is required when a load is applied to the motor as in rolling, hence increasing the mean current as a result. And the current pulsation is reduced relatively to the mean current to become almost negligible. It is necessary, therefore, to enhance the response characteristic by setting a short sampling time in such a state.
As is apparent from the above description, the sampling time needs to be changed in conformity with the load for attaining a high stability in the full operation range.
There is known a conventional speed detecting apparatus of the above-mentioned type for use in a speed change system, as disclosed in Japanese Utility Model Publication No. 53-53776. FIG. 4 is its block circuit diagram, and FIGS. 5(a), 5(b) and 5(c) show timing charts of signals for explaining the circuit operation, wherein a train of pulses .phi. of a frequency proportional to the speed are produced from a pulse generator 1 and are fed to a first counter 2 to be counted, as shown in FIG. 5(c). Meanwhile a train of clock pulses CLK of a fixed frequency obtained from another pulse generator 3 are inputted to a second counter 5 to be counted, as shown in FIG. 5(d). And upon arrival of each speed pulse .phi. from the pulse generator 1, the reset circuit 4 operates to input the count value of the second counter 5 to a register 8 and to reset the counters 2 and 5. That is, when Ns1 clock pulses CLK outputted from the pulse generator 3 arrive during the first speed pulse .phi. Ns1 clock pulses are stored in the register 8, then Ns2 clock pulses are stored during the next speed pulse .phi., and subsequently Ns3 clock pulses are stored in sequence. Accordingly, the sum Ns of the count values of the second counter 5 stored in the register 8 during the count time of the first counter 2 from zero to N.phi. is expressed as Ns=Ns1+Ns2+ . . . +Ns.phi., as shown in FIG. 5(a).
Therefore the number N of rotations is a value proportional to the number of speed pulses produced from the pulse generator 1 during a unit time, and it is expressed as ##EQU1##
Thus, the rotation speed N can be obtained through computation of Eq. (2) by inputting the content values N.phi. and Ns of the register 8 to a CPU 7, where Ka and Kb are proportional constants, and Ts is a speed measurement time corresponding to a sampling period for speed detection.
In the conventional speed detecting apparatus where the speed is determined by the number of clock pulses CLK inputted during the unit time of one pulse .phi., there exists a disadvantage that when the duration of one pulse .phi. is long to represent a low speed, the number Ns.phi. of clock pulses CLK per pulse .phi. becomes sufficiently large so that the error is small, but in case the duration of one pulse .phi. is short to represent a high speed, the number Ns1 of clock pulses CLK per pulse .phi. becomes small to eventually cause increase of the error. Accordingly the error induced in the sum Ns of Ns1, Ns2 . . . and so forth also increases at a high speed. Furthermore, when N.phi. is kept fixed, the sampling time Ts changes merely depending on the period of the signal .phi. which corresponds to the speed, and it is impossible to establish the sampling time Ts from the CPU 7 independently of the signal .phi.. In the circuit configuration where Ts can be controlled with N.phi. variable in accordance with .phi., a comparator becomes necessary for comparing the count value of the first counter 2 with a set value N.phi., hence increasing the number of component elements to eventually render the configuration complicated.